1. Field of the Invention
The present invention relates to an OTA, a squarer, a hyperbolic sine circuit, and a hyperbolic cosine circuit and more particularly, to an OTA, a squarer, a hyperbolic sine circuit, and a hyperbolic cosine circuit each of which is comprised of "floating transistors", which are suitable for a semiconductor integrated circuit (IC).
2. Description of the Prior Art
A differential amplifier circuit having a superior transconductance linearity within a comparatively wide input voltage range has been known as an "Operational Transconductance Amplifier (OTA)".
A conventional Complementary Metal-Oxide-Semiconductor (CMOS) OTA is shown in FIG. 1, which is disclosed in the document (ECT-95-4) of an electronic-circuit study group in Institute of Electrical Engineers of Japan, written by N. Takai et al., and entitled "A Proposal of Linearization Technique of CMOS-OTA", published in Jan. 19, 1995.
As shown in FIG. 1, this conventional OTA includes three n-channel MOS Field-Effect Transistors (MOSFETs) M101, M102, and 103, a p-channel MOSFET M104, a constant current source 101 supplying a constant current I.sub.B1, and a constant current sink 102 sinking a constant current I.sub.s.
When the p-channel MOSFFT M104 has a transconductance parameter .beta., the transconductance parameters of the n-channel MOSFETs M101 and M102 are equal to K.sub.12 .beta., and the transconductance parameter of the n-channel MOSFET M103 is equal to K.sub.3 .beta., where K.sub.12 and K.sub.3 are constants greater than unity.
Sources of the MOSFETs M101, M102, M103, and M104 are coupled together and further connected through the constant current sink 102 to a power supply line applied with a voltage -V.sub.SS.
Gates of the MOSFETs M101 and M102, which serve as input terminals of the conventional OTA, are applied with input voltages V.sub.1 and V.sub.2 with respect to the ground, respectively. In other words, a differential input voltage V.sub.i is applied across the gates of MOSFETs M101 and M102, where V.sub.i =V.sub.1 -V.sub.2.
Drains of the MOSFETs M101 and M102 serve as output terminals of the conventional OTA, from which a differential output current .DELTA.I is derived.
A gate of the MOSFET M103 is applied with a constant voltage V.sub.B with respect to the ground. A drain of the MOSFET M103 is connected through the constant current source 101 to a power supply line applied with a voltage V.sub.DD. The drain of the MOSFET M103 is further connected to a gate of the MOSFET M104. A drain of the MOSFET M104 is connected directly to the power supply line of V.sub.DD.
Next, the operation of the conventional CMOS OTA shown in FIG. 1 is explained below.
Although circuit analysis is disclosed in the above document, this analysis is not sufficient and therefore, the circuit operation is very difficult to be understood. The following circuit analysis was carried out by the inventor, K. Kimura.
Here, it is supposed that the channel-length modulation and the body effect are ignored and that a drain current of a MOSFET varies with respect to a gate-to-source voltage of the MOSFET according to the square law.
Then, a drain current I.sub.D of a MOSFET is typically given as the following expression (1), where .beta. is a transconductance parameter, V.sub.GS is a gate-to-source voltage, and V.sub.TH is a threshold voltage. EQU I.sub.D =.beta.(V.sub.GS -V.sub.TH).sup.2 (1)
The transconductance parameter .beta. is defined as ##EQU1## where .mu. is the mobility of a carrier, C.sub.ox is the gate-oxide capacitance per unit area, and W and L are a gate width and a gate length of a MOSFET, respectively.
The constant voltage V.sub.B is adjusted to be equal to the middle-point voltage of the first and second input voltages V.sub.1 and V.sub.2. Also, the differential input voltage V.sub.i is equal to the difference between the first and second input voltages V.sub.1 and V.sub.2. Therefore, the following equations (2) and (3) are established. ##EQU2##
From the equations (2) and (3), the following equations (2') and (3') are obtained. ##EQU3##
Here, a common source voltage at the coupled sources of the MOSFETs M101, M102, and M103 is defined as V.sub.S. Then, gate-to-source voltages of the MOSFETs M101, M102, and M103 are expressed as (V.sub.1 -V.sub.S), (V.sub.2 -V.sub.S), and (V.sub.B -V.sub.S) respectively. Therefore, using the equations (1), (2'), and (3'), drain currents I.sub.D101, I.sub.D102, and I.sub.D103 of the MOSFETs M101, M102, and M103 are given by the following equations (4), (5), and (6), respectively. ##EQU4##
On the other hand, if a drain current of the MOSFET M104 is defined as I.sub.D104, the drain currents T.sub.D101, I.sub.D102, I.sub.D103, I.sub.D104 of the MOSFETs M101, M102, M103, and M104 have the following relationship (7). EQU I.sub.D101 +I.sub.D102 +I.sub.D103 +I.sub.D104 =I.sub.B (7)
Using the above equations (4), (5), and (6), the differential output current .DELTA.I of the conventional OTA is given by the following equation (8). ##EQU5##
It is clearly seen from the equation (8) that the differential output current .DELTA.I is correctly proportional to the applied differential input voltage V.sub.i. This means that the circuit configuration shown in FIG. 1 realizes an OTA function.
The MOSFET M104 serves as a bypass transistor so that the drain currents I.sub.D101, I.sub.D102, and I.sub.D103 flow through the respective MOSFETs M101, M102, and M103 according to the square-law while satisfying the equation (7).
The drain current I.sub.D104 of the MOSFET M104 is given by the following equation (9). ##EQU6##
It is clearly seen from the equation (9) that the drain current I.sub.D104 includes a component proportional to the square of the applied differential input voltage V.sub.i (i.e., V.sub.i.sup.2). This means that a bypass current ID.sub.104 expressed by the equation (9) flows through the MOSFET M104.
Due to the condition that the drain current I.sub.D104 is greater than or equal to zero, i.e., I.sub.D104 .gtoreq.0, the operable range of the differential input voltage V.sub.i is given as the following inequality (10). ##EQU7##
In the conventional CMOS OTA shown in FIG. 1, to produce the constant voltage V.sub.B equal to (1/2) (V.sub.1 +V.sub.2), a voltage divider circuit shown in FIG. 2 is used.
As shown in FIG. 2, source-coupled, n-channel MOSFETs M114 and M115 constitute a first balanced differential pair and source-coupled, n-channel MOSFETs M116 and M117 constitute a second balanced differential pair. The transconductance parameters .beta. of the MOSFETs M114, M115, M116, and M117 are equal to each other.
The coupled sources of the MOSFETs M114 and M115 are connected to the power supply line of -V.sub.SS through a constant current sink 112 sinking a constant current 2I.sub.S. The coupled sources of the MOSFETs M116 and M117 are connected to the power supply line of -V.sub.SS through a constant current sink 113 sinking a same constant current 2I.sub.S as the constant current sink 112.
A gate of the MOSFET M114 is applied with the first input voltage V.sub.1 with respect to the ground. A gate of the MOSFET M117 is applied with the second input voltage V.sub.2 with respect to the ground. Thus, the gates of the MOSFETs M114 and M117 serve as input terminals of this voltage divider circuit.
Gates of the MOSFETs M115 and M116 are coupled together to form an output terminal of the voltage divider circuit. The voltage V.sub.B is derived from the output terminal and the ground.
Drains of the MOSFETs M114 and M117 are commonly connected to the power supply line of V.sub.DD. Drains of the MOSEETs M115 and M116 are coupled together to be connected to the coupled gates of the MOSFETs M115 and M116. The coupled drains of the MOSFETs M115 and M116 are further connected to the power supply line of V.sub.DD through a constant current source 111 supplying a same constant current 2I.sub.S as the constant current sinks 112 and 113.
The operation of the voltage divider circuit is as follows.
If drain currents of the MOSFETs M114, M115, M116, and M117 are defined as I.sub.D114, I.sub.D115, I.sub.D116, and I.sub.D117, respectively, the following equations are established therebetween. EQU I.sub.D114 +I.sub.D115 =2I.sub.S =I.sub.D116 +I.sub.D117 =I.sub.D115 +I.sub.D116
Therefore, EQU I.sub.D114 =I.sub.D116 EQU I.sub.D115 =I.sub.D117
are established, which means that a differential input voltage applied across the gates of the MOSFETs M114 and M115 is equal to that of the MOSFETs M116 and M117.
Specifically, ##EQU8##
Thus, the wanted constant voltage V.sub.B =(1/2) (V.sub.1 +V.sub.2) is outputted from the coupled gates of the MOSFETs M115 and M116 and the ground.
With the conventional CMOS OTA shown in FIG. 1, as described above, a completely linear transconductance characteristic is realized. However, there is a problem that an extra circuit is necessary to produce the middle-point voltage of the first and second input voltages V.sub.1 and V.sub.2, i.e., the constant voltage V.sub.B. The extra circuit makes the circuit configuration complicated and enlarges the circuit scale.
FIG. 3 shows a conventional circuit capable of realizing a hyperbolic cosine function and a hyperbolic sine function, which is created by the inventor, K. Kimura. This circuit is disclosed in the Japanese Non-Examined Patent Publication No. 7-200710 published in 1995, which corresponds to the U.S. Pat. No. 5,754,076 issued on May 19, 1998.
As shown in FIG. 3, emitter-coupled npn-type bipolar transistors Q201 and Q202 constitute a first balanced differential pair, and emitter-coupled npn-type bipolar transistors Q203 and Q204 constitute a second balanced differential pair.
The emitter of the transistor Q201 is connected to the ground through a constant current sink 201 sinking a constant current I.sub.0. The transistor Q201 is driven by the constant current I.sub.0. The emitter of the transistor Q202 is connected to the ground through a current mirror subcircuit 203 supplying a mirror current I.sub.1 equal to a collector current I.sub.C202 of the transistor Q202.
Similarly, the emitter of the transistor Q204 is connected to the ground through a constant current sink 202 sinking a same constant current I.sub.0 as the constant current sink 201. The transistor Q204 is driven by the constant current I.sub.0. The emitter of the transistor Q203 is connected to the ground through a current mirror subcircuit 204 supplying a mirror current I.sub.2 equal to a collector current I.sub.C203 of the transistor Q203.
Bases of the transistors Q201 and Q204 are coupled together. Bases of the transistors Q202 and Q203 are coupled together. A differential input voltage V.sub.i is applied across the coupled bases of the transistors Q201 and Q204 and the coupled bases of the transistors Q202 and Q203.
Collectors of the transistors Q201 and Q204 are connected to a power supply line applied with a power supply voltage V.sub.CC. Collectors of the transistors Q202 and Q203 serve as output terminals of the conventional circuit shown in FIG. 3.
Next, the operation of the conventional circuit shown in FIG. 3 is explained below.
Supposing that the base-width modulation (i.e., the Early voltage) is ignored and that the common-base current gain factor of a bipolar transistor is equal to unity, a collector current I.sub.C of a bipolar transistor is typically given as the following expression (11). ##EQU9##
In the expression (11), V.sub.BB is a base-to-emitter voltage of the bipolar transistor, and I.sub.s is a saturation current thereof. Also, V.sub.T is the thermal voltage defined as V.sub.T =kT/q, where k is the Boltzmann's constant, T is absolute temperature in degrees Kelvin, and q is the charge of an electron.
In the first differential pair, the transistor Q201 is driven by the constant current I.sub.0 and the transistor Q202 is driven by the variable current I.sub.1 equal to the collector current I.sub.C202. Therefore, a collector current I.sub.C201 of the transistor Q201 is expressed as follows, where V.sub.BE201 is a base-to-emitter voltage of the transistor Q201. ##EQU10##
Accordingly, the collector current I.sub.C202 of the transistor Q202 is expressed as follows, where V.sub.BE202 is a base-to-emitter voltage of the transistor Q202. ##EQU11##
It is seen that the equation (13) is in a same form as that of the equation (11), in which the saturation current I.sub.S is replaced with the constant current I.sub.0 and the base-to-emitter voltage V.sub.BE is replaced with the differential input voltage (-V.sub.i). This means that the transistor Q202 serves as a "floating transistor" that operates independent of the power supply voltage V.sub.CC and the ground potential.
Similarly, in the second differential pair, the transistor Q204 is driven by the constant current I.sub.0 and the transistor Q203 is driven by the variable current I.sub.2 equal to the collector current I.sub.C203. Therefore, a collector current I.sub.C204 of the transistor Q204 is expressed as follows, where V.sub.BE204 is a base-to-emitter voltage of the transistor Q204. ##EQU12##
Accordingly, the collector current I.sub.C203 of the transistor Q203 is expressed as follows, where V.sub.BE203 is a base-to-emitter voltage of the transistor Q203. ##EQU13##
It is seen that the equation (15) also is in a same form as that of the equation (11), in which the saturation current I.sub.S is replaced with the constant current I.sub.D and the base-to-emitter voltage V.sub.BE is replaced with the differential input voltage V.sub.i. This means that the transistor Q203 serves as a "floating transistor" that operates independent of the power supply voltage V.sub.CC and the ground potential.
If the sum of the collector currents I.sub.C202 and I.sub.C203 is defined as I.sup.+ and the difference between the collector currents I.sub.C202 and I.sub.C203 is defined as I.sup.-, the sum and difference currents I.sup.+ and I.sup.- are given by the following equations (16) and (17), respectively. ##EQU14##
As clearly seen from the equations (16) and (17), the sum current I.sup.+ is proportional to a hyperbolic cosine (cosh) of the differential input voltage V.sub.i, and the difference current I.sup.- is proportional to a hyperbolic sine (sinh) of the differential input voltage V.sub.i.
In other words, if the sum current I.sup.+ is used as an output of the conventional circuit shown in FIG. 3, a hyperbolic cosine circuit is realized. If the difference current I.sup.- is used as an output of the conventional circuit shown in FIG. 3, a hyperbolic sine circuit is realized.
With the conventional circuit shown in FIG. 3, a bootstrap operation is realized by using the two current mirror subcircuits 203 and 204. Therefore, there is a problem that unignorable error will occur if the mirror ratios of the current mirror subcircuits 203 and 204 are different from each other.
An OTA and a squarer are essential, basic function blocks in analog signal applications. In recent years, there has been the strong need of realizing the transconductance linearity of an OTA and of realizing the square-law characteristic of a squarer within a practically wide input voltage range.
Also, to perform signal processes used in the neural computing or neural networks by analog circuits, hyperbolic cosine (cosh) and hyperbolic sine (sinh) circuits are necessary.